Circuit design and analysis for emerging nonvolatile memory technology

Memory has become an essential product in our modern world, due to the increasing amount of available data. Currently, there are 3 main types of memory: Static RAM (SRAM), Dynamic RAM (DRAM), and Flash memory. Though the performance of these technologies keeps improving, they are still becoming the...

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Bibliographic Details
Main Author: Kurniawan, David Orlando
Other Authors: Goh Wang Ling
Format: Final Year Project
Language:English
Published: 2017
Subjects:
Online Access:http://hdl.handle.net/10356/71598
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Institution: Nanyang Technological University
Language: English
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Summary:Memory has become an essential product in our modern world, due to the increasing amount of available data. Currently, there are 3 main types of memory: Static RAM (SRAM), Dynamic RAM (DRAM), and Flash memory. Though the performance of these technologies keeps improving, they are still becoming the system performance bottleneck because they still cannot match the speed of logic gates. Memory also consumes a large portion of energy, while being volatile. Furthermore, CMOS scaling is approaching the fundamental limits where transistors may not shrink further. All these problems raise the need of new memory type which can address the issues. Recently, there are potential emerging Non-volatile Memory (NVM) technologies. They are Phase-Change RAM (PCRAM), Spin-transfer-torque Magnetic RAM (STT-MRAM), and Resistive RAM (RRAM). These technologies offer high-density and high-speed cells as DRAM while being non-volatile as Flash. They also exhibit high on-off ratio and potential low-energy characteristics. These features make NVM technologies attractive to be regarded as current memory technologies’ successors, especially for embedded devices purposes. This project aims to design a selected NVM for low power usage. In the beginning, analysis is done to compare the advantages and disadvantages of each NVM compared to other existing memories. A conclusion is drawn based on the analysis, and a selected NVM is chosen for further analysis. Finally, a complete circuit is designed for both read and write operations of the NVM. This circuit is optimised to achieve low power consumption while not sacrificing the access time.