High speed ADC

• Main Author: Lin, Esmond Chengyuan
• Other Authors: Chang, Joseph Sylvester
• Format: Final Year Project
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/71830
• Institution: Nanyang Technological University

This report presents a simulation model design of a 10-bits pipelined ADC with background calibration. The proposed architecture includes a 3-bit ADC, five 1.5-bits ADC and a 2-bit ADC in a cascade. Some non-ideal errors and offsets are introduced in the pipelined ADC during simulation to model the...