High speed ADC

• 主要作者: Lin, Esmond Chengyuan
• 其他作者: Chang, Joseph Sylvester
• 格式: Final Year Project
• 語言: English
• 出版: 2017
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: http://hdl.handle.net/10356/71830
• 機構: Nanyang Technological University

This report presents a simulation model design of a 10-bits pipelined ADC with background calibration. The proposed architecture includes a 3-bit ADC, five 1.5-bits ADC and a 2-bit ADC in a cascade. Some non-ideal errors and offsets are introduced in the pipelined ADC during simulation to model the...