Accelerator of convolution neural networks based on FPGA

• Main Author: Yu, Guohao
• Other Authors: Goh Wang Ling
• Format: Theses and Dissertations
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/72593
• Institution: Nanyang Technological University

Recent years, with the development of Convolution Neural Networks (CNN), machine learning has achieved great success in many areas such as speech recognition, vision classifications, face recognition and other kinds of pattern recognitions. In general, CNN is a kind of deep learning, which imitates the way human beings process the signal from nature. The algorithm of CNN mainly includes two parts: multiplication and summation, which is also called a convolution layer. Multiple convolution layers are involved to implement the whole CNN, on each layer, the raw data or the result from the former layer is used to do convolution with the filter of which the factors are gained from the software training. After several layers processing, the final output signal justifies the samples like the voice or images and give people a feedback or send an instruction to other systems. Traditional CNNs usually operate on Central Processing Unit (CPU) or Graphics Processing Unit (GPU); however, as the functions become more and more complex and requirements of performance including power consumption and speed are increasingly high, a new way to realise it on Field-Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) appeared. It also indicates that CNN is going to be more portable in the future. This dissertation is to provide a general used accelerator of CNN on FPGA; meanwhile a new structure is proposed to balance the performance and the usage of the resources. This work operates on an evaluation board ZYNQ-7 ZC702 of Xilinx. A CNN structure is mapped on the FPGA device, the Acorn RISC Machine (ARM) core is used to control the camera to capture the images and the data flow in this whole system.