Data-driven dynamic logic for low power adders and multipliers
In today’s world, all the electronic devices are expected to operate with high speed, low power dissipation, occupying lesser area and show higher performance. To ensure these criteria, there are many logics proposed for digital circuit implementation. For high speed operation, clocks are mandatory...
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2018
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| 在線閱讀: | http://hdl.handle.net/10356/73110 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | In today’s world, all the electronic devices are expected to operate with high speed, low power dissipation, occupying lesser area and show higher performance. To ensure these criteria, there are many logics proposed for digital circuit implementation. For high speed operation, clocks are mandatory in digital circuits. In case of dynamic logic, the presence of clock, increases the speed but causes higher power dissipation. To mitigate this problem, Data Driven Logic (D 3L) implementation is proposed, where the combination of input data is provided as the clock signal, thus not affecting the speed and reducing the power dissipation simultaneously. This dissertation project discusses about, the design, implementation and simulation of Full Adders using Static, Dynamic Domino, NP-CMOS, D 3L and Dual Rail Data Driven Dynamic Logic circuits. 8-Bit Full Adder, 4x4 Array Multiplier and 8x8 Array Multiplier are considered for performance analysis. These circuits are designed and simulated using Cadence Virtuoso in TSMC 65nm specification. The propagation delay and power of each logic is calculated and compared. The comparison shows an improved performance for D 3L circuits with respect to speed, area and power. |
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