Data-driven dynamic logic for low power adders and multipliers
In today’s world, all the electronic devices are expected to operate with high speed, low power dissipation, occupying lesser area and show higher performance. To ensure these criteria, there are many logics proposed for digital circuit implementation. For high speed operation, clocks are mandatory...
Saved in:
Main Author: | Mahendiran Navasakthi |
---|---|
Other Authors: | Lau Kim Teen |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2018
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/73110 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Low power low voltage adder cells for digital multiplier
by: Zhang, Mingyan
Published: (2008) -
Low power data-driven dynamic logic circuits
by: Zhang, Han
Published: (2015) -
Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits
by: Prasanna Dhayalan
Published: (2015) -
Modulo adders, multipliers and shared-moduli architectures for moduli of type
by: Shibu, Menon
Published: (2008) -
Design of ultra low power 1-bit full adder cell for logic devices
by: Kumar, Abhishek
Published: (2019)