An enhanced low-power high-speed adder for error-tolerant application

• Main Authors: Zhu, Ning, Goh, Wang Ling, Yeo, Kiat Seng
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/93564; http://hdl.handle.net/10220/6350; http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403865
• 機構: Nanyang Technological University

The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI desi...