DPLL system modeling and design aspects

• Main Author: Dodamani Ravikiran
• Other Authors: Navaneethan Venkadasamy
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73149
• Institution: Nanyang Technological University

The growing demand for wireless device in military and communication applications in today’s technological world has made phase locked loop (PLL) an essential component of many electronic devices, it can be employed as frequency synthesizers, for amplitude and frequency demodulator and clock data recovery. The frequency synthesizers are widely used to generate signal whose frequency is equal to multiple of reference frequency by using single oscillator. The first PLL was introduced in 1965 which was completely analog. Due to the significant drawbacks in traditional analog phase locked loop (APLL) as slow synchronization at the start of PLL and expensive components of VCO and filter has made DPLL gain more attention [1]. This thesis presents system modeling and design aspects of DPLL. The design aspects are studied and implemented in frequency domain to have a stable loop with good gain and phase margin. DPLL is similar in structure as analog PLL with time to digital converter (TDC) replacing phase detector and charge pump, digital loop filter (DLF) replacing analog loop filter and digital controlled oscillator (DCO) replacing voltage controlled oscillator. The specification for DPLL implementation consist of, TDC resolution of 10ps, input reference frequency of 19.2MHz, DCO tuning range of 30MHz and divide ratio of 166. The first order DLF for type-I PLL is designed during dissertation work and frequency analysis are performed. The DLF design involves first order filter implementation as differentiator and as moving average filter. The performance of type-I PLL is enhanced by DLF implementation which results stable loop, good gain and phase margin and stable step response. From the frequency analysis, the obtained bandwidth is approximately 15kHz and phase margin is 89.97deg. This thesis also covers system modeling of DPLL which is performed as time domain analysis. This involves modeling of TDC, DLF, DCO and divider in Verilog-A. In DCO modeling, fixed inductance of 3.5nH and DCO operating frequency of 3.2GHz are considered. Based on this the variable capacitance value and fixed capacitance value are calculated and modeled. Finally, the closed loop analysis of type-I PLL for different DLF implementation is performed and analyzed. The locking of DPLL is properly obtained with different DLF designs. The thesis also covers the circuit level implementation of TDC, MMD and second order DLF which are modeled from leaf level hierarchy. As a part of DPLL study, circuit level implementation of all blocks are explained in detail.