Accelerating design space exploration of two-level exclusive cache hierarchy

• Main Author: Leong, Leonard Jia Wen
• Other Authors: Arvind Easwaran
• Format: Final Year Project
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/73854
• Institution: Nanyang Technological University

Embedded systems are getting popular in today’s world. They are usually small and thus have a limited energy storage. Being able to reduce energy consumption will mean an increase in the lifetime of the device. The bulk of energy consumption in an embedded system is typically by the CPU and one good place to target a reduction of energy consumption of the CPU is to target the cache. Our plan of optimization is to reduce cache usage without impacting performance and this will be achieved by trying to find and use optimal cache settings, in the form of optimal cache set size and associativity. In the current world, having to find these optimal cache settings takes a lot of time and effort. Even the fastest known algorithm still takes a substantial amount of time to process and is targeted at single-level caches at a time when multi-level caches are getting common. After an attempt at a cache simulator using look-up table returned disappointing results, the next step was the use of parallel processing to simulate multiple cache settings simultaneously, and while the processing time was fast there were issues like race condition that had to be dealt with. Finally, It is believed that the findings from this project would help on the investigation path of shortening the time-to-market for embedded processor and also to reduce initial production costs.