Design of variation-tolerant integrated circuits

• Main Author: Jayakrishnan, Mini
• Other Authors: Kim Tae Hyoung
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/73872
• Institution: Nanyang Technological University

The semiconductor industry is strategically focusing on automotive markets and significant investment is targeted to address these markets. Run time better-than-worst-case designs like Razor leads to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. In this work, we propose four resilient processor subsystems which incorporate slack balancing circuits to relax the timing margins of a processor pipeline based on the available slack. Together with logic under-design, the proposed methodology results in power and area savings compared to worst-case design techniques. The presence of slack balancing circuits ensures correct functionality of the design at worst operating conditions. Based on this, we propose the first subsystem to utilize positive slack available in the pipeline stages using Slack Balancing Flip-flops (SBFFs) and re-distributes it to the preceding error-prone critical paths. SBFF has a redundant latch to sample the late arriving data. We reshape the SBFF fan-in cone by downsizing the logic to achieve power and area savings of 12% and 8%, respectively, as compared to the worst-case design. Our second subsystem uses library based power optimization techniques together with SBFFs. Here we prune the SBFF standard cell library to filter out the power-hungry cells. In addition to this, we use Better than Worst-case (BTWC) sigma corner library to under-design the logic whose slack margins are relaxed by the SBFFs. This gave a power and area savings of 47% and 3%, respectively, in the execute pipeline stage. The third subsystem provides a Clock Stretching Flip-flop (CSFF) to remove the redundancy inside SBFFs for better power and area savings. The combination of CSFFs, multi-bit flip-flops (MBFFs), logic reshaping and BTWC sigma corner libraries resulted in a power and area savings of 32% and 16%, respectively, in the fetch pipeline stage and 69% and 15%, respectively, in the execute pipeline stage when compared to the traditional worst-case design. In the fourth subsystem, we use Data-dependent Clock Stretching Flip-flop (DDCSFF) in addition to simple CSFFs to replace the critical endpoints with sufficiently low activity rates. Here we use logic reshaping for power optimization together with CSFFs and DDCSFFs. Experiment results showed power and area savings of 70% and 9.5%, respectively, in the execute pipeline stage with respect to the worst-case design. For all the proposed subsystems, the critical logic power minimization method relaxes the slack margins of all the timing paths including the short paths converging into the SBFF. The timing budgeting and timing correction using opportunistic slack eliminates critical operating point behaviour, meta-stability issues and hold buffer overheads encountered in existing resilience techniques.