Design and implementation of a digital integrated circuit for logarithmic conversion (AS6)
This report describes the implementation of the Abed & Siferd’s 6-region logarithmic approximation (AS6) algorithm in digital integrated circuit. The design was first coded in Verilog HDL and verified for functionality using ModelSim simulations. The sub-blocks of the logarithmic converter were...
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Format: | Final Year Project |
Language: | English |
Published: |
2011
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Online Access: | http://hdl.handle.net/10356/46037 |
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Institution: | Nanyang Technological University |
Language: | English |