Design and implementation of a digital integrated circuit for logarithmic conversion (AS6)

• Main Author: Ne Kyaw Zwa Lwin
• Other Authors: Jong Ching Chuen
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/46037
• Institution: Nanyang Technological University

This report describes the implementation of the Abed & Siferd’s 6-region logarithmic approximation (AS6) algorithm in digital integrated circuit. The design was first coded in Verilog HDL and verified for functionality using ModelSim simulations. The sub-blocks of the logarithmic converter were written separately, and combined at the top level block. All sub-blocks were designed in behaviour model except the 6-region error correcting circuit. The purpose is to preserve the original algorithm and circuit topology. The Verilog model was then synthesized into gate-level using Synopsys Design Compiler. Design constraints were set to achieve the best timing and area. After the design was synthesized, it achieved a maximum clock frequency. The netlist and constraints from the synthesis were then used for placement and routing. The design was placed and routed in Cadence SoC Encoutner environment. At the end of this stage, timing and power analysis were done. The routed design is also verified against the functional design with simulation. The detail of the RTL design, functional simulation, synthesis, and physical design are described in the report. Some recommendations for the future work are also included.