Design and implementation of a digital integrated circuit for logarithmic conversion (AS6)

• المؤلف الرئيسي: Ne Kyaw Zwa Lwin
• مؤلفون آخرون: Jong Ching Chuen
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2011
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/46037

This report describes the implementation of the Abed & Siferd’s 6-region logarithmic approximation (AS6) algorithm in digital integrated circuit. The design was first coded in Verilog HDL and verified for functionality using ModelSim simulations. The sub-blocks of the logarithmic converter were...