Design and implementation of a digital integrated circuit for logarithmic conversion (AS6)

• Main Author: Ne Kyaw Zwa Lwin
• Other Authors: Jong Ching Chuen
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/46037
• Institution: Nanyang Technological University

This report describes the implementation of the Abed & Siferd’s 6-region logarithmic approximation (AS6) algorithm in digital integrated circuit. The design was first coded in Verilog HDL and verified for functionality using ModelSim simulations. The sub-blocks of the logarithmic converter were...