Design a 16-bit Low power multiplier

• Main Author: Gu, Bin
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/74771
• Institution: Nanyang Technological University

Digital integrated circuit devices are always playing a very important part in the electronic system. As the technology development, the requirements for digital system are getting higher. High in speed, low dissipation in power and less in cost are always the most demanded. Design of a digital Multiplier is a very old topic in digital integrated circuit design. This project is aiming to use HDL and Synopsys IC design tools to design a 16-bit Low Power Multiplier. We will have two designs, one is a dynamic 16-Bit Braun Multiplier and the other is a 16-bit Sequential Multiplier. By the comparison of the result, we are going to find a better design for low power consumption. By the comparison of the result from these two design. We can find that the Sequential Multiplier has a better performance in power consumption and it is also much easier to design and more programmable than the Braun Multiplier. The purpose of this project is to master the application the Verilog HDL more skillfully and get a better understanding in Digital IC Design Process Flow.