Variation aware memory design for low-power application

• Main Author: Yao, Minglin
• Other Authors: Kong Zhi Hui
• Format: Final Year Project
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/74914
• Institution: Nanyang Technological University

With the continual development and advancement of technology, there is increasing demand for ultra-low power, area efficient, reliable, and high-performance silicon integrated circuit (IC). Static Random-Access Memory(SRAM) has been widely used due to its faster speed, lower power consumption which are the core parameters to determine the merit of a circuit. In this project, A comprehensive performance evaluation of the existing memory cell designs are reviewed and an ultra-low voltage and a 9T SRAM with improved read and transistor optimization is proposed. 9T Sleep Mode SRAM with improved read delay and Vt optimization are designed for memory cell that operates at standby mode for most of the time. The hold power dissipation over a long period of time will hardly outweigh the power dissipation during read and write operation. Hence, the total power dissipation over a period has greatly reduced. There are other improvements on the key parameters. In comparison with conventional 6T SRAM, SNM stability has improved by 11%, 41% improved worst-case read access delay, 7.6% improved worst-case write delay and a 24% reduction in the total power dissipation over a period of 300ps.