Ultra-low power energy harvesting and power management circuits for IoT applications

• Main Author: Karim Hany Mohamed Mohamed Rawy
• Other Authors: Kim Tae Hyoung
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/75898
• Institution: Nanyang Technological University

Recent progress in integrated circuits (IC) technology and design techniques, especially in ultra-low power circuits domain, has led a rapid growth of fully integrated and portable electronics within internet of things (IoT) smart nodes and wearable sensors system on chip (SoC). IoT applications including biomedical sensors, body area networks and wireless sensors, have taken advantage of such a progress. However, with the increase of people needs, numerous blocks must be integrated within the IoT SoC. Hence, a compact, efficient and self-sustained power management circuit (PMC) with a long life-time design becomes crucial for IoT SoC. Thus, energy scavengers, such as photovoltaic cells (PV), thermos-electric generators (TEG) and electro-static harvesters, become an attractive solution to power the PMC, for self-sustaining and prolonged life time systems. Switched capacitor charge pump (SCCP) along with low drop out (LDO) regulators are an adequate solution for PMC within energy harvesting systems (EHS) for their integrability on-chip, avoiding bulky off-chip inductors, especially for implantable biomedical applications. However, these regulators must be controlled with a maximum power point tracking (MPPT) system to maximize the energy being harvested and to store it efficiently. It should be noted that the MPPT control the regulators whether to maximize the harvested power transfer as per load demand, or to condition the regulator to harvest the maximum available power from the energy harvester. For instance, many MPPT have been developed to track the maximum power point to maximize the tracking efficiency and/or the conversion efficiency.x Several requirements that should be met are wide input voltage handling, wide output load range coverage, output voltage regulation and ultra-low power consumption. The latter one is of a great concern to maximize the EHS overall efficiency and extend its lifetime in case of battery powered PMC. In the first part of this thesis, I propose a novel ultra-low power MPPT technique with a wide tracking range. The proposed technique is an indirect, noninterrupting approach using a novel timing-based algorithm addressing the tracking efficiency. The proposed time-based MPPT technique is self-adaptive and applicable to several types of PVs and TEGs without external reconfiguration or change of passive components. It reduces the power consumption and design complexity. It consists of an ultra-low power digital processing unit to execute the proposed timingbased algorithm along with an ultra-low power window comparator to track the maximum open circuit voltage (Vmpp) without the need to voltage references, perturbation steps and power-hungry voltage or current sensors. In addition, a variable gain is employed using a one-hot barrel shift register to reduce the transient response time in case of an abrupt input voltage change. A test chip was fabricated in 65-nm CMOS technology. The test chip can harvest energy with the input voltage range of 0.4 V to 1.7 V and the step response time of less than 100 ms at the minimum supply voltage of 0.8 V. The tracking efficiency is up to 96.2 % when supplied by a photovoltaic (PV) micro-cell array using an irradiation range of 200 lux to 1000 lux. In the next part of this thesis, a three-dimensional MPPT (3-D MPPT) technique is proposed, addressing the conversion efficiency, for ultra-low power EHS within IoT smart nodes. The proposed MPPT improves the conversion efficiency overxi a wide load range using a novel switch width modulation (SWM) technique. It enhances the conversion efficiency at ultra-light load condition by eliminating the trade-off between the gate driver and conduction loss. The proposed SWM technique modulates the SCCP transistors size in proportion to the load condition, input voltage and the swing voltage applied. The tested chip, fabricated in 65-nm CMOS technology, can harvest from 0.35 V and provides a regulated output voltage at 1 V with peak efficiency of 88% at 200 µW and conversion efficiency > 60% at 100 nW. The last part of this thesis devoted to a fully integrated, low voltage digital lowdropout voltage (DLDO) regulator for ultra-low power applications with a load current aware clock modulation scheme. The proposed DLDO presents a novel clock modulation scheme that enhances the trainset performance without degrading the overall DLDO current efficiency. The proposed clock modulation (CM) increases the clock frequency when the load current changes abruptly eliminating the speedefficiency trade-off using a fixed clock frequency. Thus, it enhances the transient response performance without sacrificing the current efficacy. The proposed DLDO chip is fabricated using 65-nm CMOS technology. It operates at 0.6 V voltage supply with 50mV dropout voltage. It achieves of 99.7% as current efficiency with load current range 10 μA to 200 μA and the quiescent current 0.9 μA.