Timing mismatch calibration circuit for high-speed time-interleaved ADCs

• المؤلف الرئيسي: Liu, Yifei
• مؤلفون آخرون: Chang Joseph Sylvester
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2018
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/76014

The concept of a Time-Interleaved analog-to-digital converter (TI ADC) which comprises sub-ADCs (channels) is proposed as a means of increasing the speed of analog-to-digital converters (ADCs), albeit with a power and area penalty. During the alternate sampling process, timing mismatch between th...