Analysis and architecting of hierarchical DFT flow

• المؤلف الرئيسي: Mittal, Richa
• مؤلفون آخرون: Gwee Bah Hwee
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2018
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/76064
• المؤسسة: Nanyang Technological University

Design for Test (DFT) is a critical activity in the modern System on Chip designs as the complexity of the chip is increasing. Generating test patterns for the current and upcoming devices having huge designs is again becoming a challenge which needs to be addressed. Hierarchical DFT is one such...