Analysis and architecting of hierarchical DFT flow

• Main Author: Mittal, Richa
• Other Authors: Gwee Bah Hwee
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76064
• Institution: Nanyang Technological University

Design for Test (DFT) is a critical activity in the modern System on Chip designs as the complexity of the chip is increasing. Generating test patterns for the current and upcoming devices having huge designs is again becoming a challenge which needs to be addressed. Hierarchical DFT is one such approach which allows DFT insertion and Pattern Generation at core-level to be mapped on the top-level. This enhances core-reusability and saves development times of large SoCs having a large number of IPs. This dissertation aims at developing Hierarchical DFT flow using core wrapping methodology. It starts with the DFT insertion in the core which includes a balanced number of wrapper chains and internal scan chains. The concept of wrapper chains is explored by implementing dedicated and shared wrapper cells and using them in two different flows: Dedicated flow and Maximized Reuse flow. The core is wrapped considering the test compression applied in the design as the compressed flow includes additional logic. The flow includes the ATPG run over the DFT inserted netlist. The internal and external mode patterns are generated and written in a PATDB format. The fault list is saved and the core description is saved in a .tcd file. These are retargeted on a top level SoC wrapper which contains multiple core instantiations and small top-level combinational logic. The patterns are generated at the top level and written in an STIL file. The patterns are verified and ported to ATE for silicon production tests. However, the flow associated with hierarchical DFT is quite complex with various competing requirements. DFT metrics like coverage, Test times, Runtimes, Design area, Development times and Verification effort need to be considered. Hence, various configurations are evaluated in these terms to recommend the best approach for implementing hierarchical DFT.