Analysis and architecting of hierarchical DFT flow

Design for Test (DFT) is a critical activity in the modern System on Chip designs as the complexity of the chip is increasing. Generating test patterns for the current and upcoming devices having huge designs is again becoming a challenge which needs to be addressed. Hierarchical DFT is one such...

全面介紹

Saved in:
書目詳細資料
主要作者: Mittal, Richa
其他作者: Gwee Bah Hwee
格式: Theses and Dissertations
語言:English
出版: 2018
主題:
在線閱讀:http://hdl.handle.net/10356/76064
標簽: 添加標簽
沒有標簽, 成為第一個標記此記錄!