Optimizing control architecture for next generation cellular transceivers by introducing performance accelerator

• Main Author: Sandesh Pakhale
• Other Authors: Andreas Herkersdorf
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76066
• Institution: Nanyang Technological University

There is a growing demand for wireless communication. The present cellular modem technology, i.e., 4G Long Term Evolution is not being able to meet this demand. 4G LTE is unable to provide quick updates on the antenna of a handset i.e. signals from a downlink are not decoded and acknowledged to the base station within a short turnaround time. Shorter turnaround time is needed to cater to high throughput and low latency applications. The power control algorithm present in the cellular modem is responsible for the decoding and acknowledgment of the signal. A new technology, i.e., 5G New Radio standard is needed, in which the turnaround time should be within 10s of μsec as compared to 100s of μsec in 4G LTE. Thus, approximately 90% improvement is needed in the power control algorithm. To get this improvement, the power control algorithm needs to be optimized. Optimizing the power control algorithm means optimizing the elements of the RF processing unit in the cellular modem. Optimization of the power control algorithm can be achieved by implementing hardware accelerators and parallelizing the instruction execution in the processors present in the RF processing unit.