Optimizing control architecture for next generation cellular transceivers by introducing performance accelerator
There is a growing demand for wireless communication. The present cellular modem technology, i.e., 4G Long Term Evolution is not being able to meet this demand. 4G LTE is unable to provide quick updates on the antenna of a handset i.e. signals from a downlink are not decoded and acknowledged to the...
Saved in:
Main Author: | Sandesh Pakhale |
---|---|
Other Authors: | Andreas Herkersdorf |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2018
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/76066 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Energy-efficient hardware accelerators based on bit-serial graph and memory-centric computing architectures
by: Mu, Junjie
Published: (2023) -
FPGA based prototyping of UART block in GNSS transceiver
by: Raju Jipson
Published: (2018) -
Ultra Wideband - Circuits, Transceivers and Systems
by: Gharpurey, Ranjit
Published: (2017) -
CMOS quadrature voltage-controlled oscillators and generators for wideband and multi-band transceivers
by: Xie, Juan
Published: (2011) -
Ultra lower power transceiver board demo
by: Yao, Zhenqiu
Published: (2022)