Improvement in speed performance through transistor process optimization
This thesis presents the means to achieve higher speed yield for CMOS logic circuits through transistor optimization. Experiments were carried out to study the effect of each process condition on transistor drive current and its timing parameter. Based on the obtained results, selection of process c...
Saved in:
Main Author: | |
---|---|
Other Authors: | |
Format: | Theses and Dissertations |
Published: |
2008
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/4046 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |