Improvement in speed performance through transistor process optimization
This thesis presents the means to achieve higher speed yield for CMOS logic circuits through transistor optimization. Experiments were carried out to study the effect of each process condition on transistor drive current and its timing parameter. Based on the obtained results, selection of process c...
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/4046 |
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| Institution: | Nanyang Technological University |
| Summary: | This thesis presents the means to achieve higher speed yield for CMOS logic circuits through transistor optimization. Experiments were carried out to study the effect of each process condition on transistor drive current and its timing parameter. Based on the obtained results, selection of process conditions to achieve desired transistor drive current are presented. A linear model has been developed to predict the transistor drive current based on in-line measurement data. |
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