FPGA based prototyping of UART block in GNSS transceiver
System-on-Chip devices are getting more complex with multiple IP blocks. As such, IP validation plays a major role in mitigating IP bugs which lead to the chip failure. Tough it is not possible to completely eliminate this problem, but with FPGA based prototyping can be tested with reasonable speed...
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| Format: | Theses and Dissertations |
| Language: | English |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10356/76067 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | System-on-Chip devices are getting more complex with multiple IP blocks. As such, IP validation plays a major role in mitigating IP bugs which lead to the chip failure. Tough it is not possible to completely eliminate this problem, but with FPGA based prototyping can be tested with reasonable speed and accuracy in many aspects of design. In this project FPGA based prototyping of UART GNSS transceiver IP block using Intel Arria 10 FPGA is reported. The complex SOC design is implemented in FPGA to give maximum view on both hardware and software. Different design constraints were incorporated in FPGA emulation of the UART block, which gives user the flexibility to validate the design as per their requirement. |
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