Switch cell optimization for power gated design

• Main Author: Somani Ronak Kailashbhai
• Other Authors: Lim Meng Hiot
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/76077
• Institution: Nanyang Technological University

One of the key features for the success of hand-held devices is their low power consumption. For complex architecture and high frequency computation, reducing chip power dissipation has become ever more important. Various techniques like Multi threshold, dynamic voltage and frequency scaling (DVFS) and clock gating are used to limit the dynamic power. But for lower node technologies, leakage power has become a major contributing factor in total power and can no longer be neglected. Power gating methodology is implemented to prevent leakage power dissipation. Switch cells turns on or off the power supply of a block, reducing leakage power. Implementing a power-gated block with optimized number of switch cells is vital to achieve power target. IR drop, turn-off power and area-overhead also depends on the number of switch cells inserted. Therefore, it is important to place an optimal number to meet performance, power and area desired. This dissertation attempts at finding the optimal number of switch cells by studying different parameters over a hardware design used for connected home application.