Design of 128-Bit asynchronous-logic AES processor

• Main Author: Chua, Elton Yi Wei
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2019
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits; DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
• Online Access: http://hdl.handle.net/10356/77615
• Institution: Nanyang Technological University

Cryptography is the practice of transmitting information securely, with the 4 objectives of information confidentiality, data integrity, non-repudiation and authentication. Modern encryption methods use mathematical algorithms to convert the plaintext into ciphertext, which can only be decrypted successfully by the intended reader. Advanced Encryption Standard (AES) is the most popular encryption method in use today, and it has proven resilient to software brute force attacks. However, research has suggested that Side Channel Attacks that target the hardware vulnerabilities of the AES processor can be effective. In response, Asynchronous circuit design has been proposed to reduce the effectiveness of Side Channel Attacks. This project establishes a methodology to design a 128-Bit Asynchronous-Logic AES processor, allowing for quicker simulation and benchmarking of different Asynchronous designs. This methodology consists of 4 steps: characterization of basic cells, creating an asynchronous cell library, converting the synchronous AES processor to an asynchronous netlist, and running simulations for the asynchronous AES processor.This project has successfully characterized 5 basic cells and 7 asynchronous cells, tested the synchronous to asynchronous netlist conversion tool, and ran simulations for a simple asynchronous AES processor module.