Radiation hardened CMOS design

• Main Author: Di, Jiwei
• Other Authors: Lau Kim Teen
• Format: Theses and Dissertations
• Language: English
• Published: 2019
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/77790
• Institution: Nanyang Technological University

Nowadays, human beings have stepped into space era gradually. However, space environment is highly radioactive, which means electronic devices will suffer from space-radiation effect, especially most modern semiconductor electronic elements are vulnerable to radiation damage. It is obviously that a little bit of instability of equipment in out-space may cause disaster and the lack of high-performance radiation-hardened chips used in space is already lag behind the most recent development. So, in this dissertation project I am trying to design a high-performance radiation-hardened chips used in space. There are two major radiation sources, TID and SEE. SEE could be further divided into single event upset, single event transient, single event latchup. For various approaches to prevent radiation effect, two main ways could be taken, radiation hardened by process or by circuit design. Due to radiation hardened by process is impractical for mass fabrication industry, by circuit design is the core of work and research. In order to deal with Total Ionizing Dose effect, there are three different methods put forward, Large Size Design, Radio Logic Circuit, and Enclosed Layout Transistors. What’s more, for the sake of preventing SEE, Triple Modular Redundancy, DICE with improved structure, self-stop circuit and self-recovery circuit are discussed respectively. With the purpose to combined all the technologies together, a complete radiation hardened system is come up. Overall, this dissertation project proposes several useful approaches to deal with the radiation damages detection and protection circuit design.