A low-quiescent and low dropout regulator in 40nm CMOS

• Main Author: Pu, Kai Lin
• Other Authors: Chan Pak Kwong
• Format: Final Year Project
• Language: English
• Published: 2019
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/78348
• Institution: Nanyang Technological University

Low Dropout (LDO) voltage regulator is a fundamental unit in power management ICs for system-on-chip (SoC) applications which is very popular nowadays. An LDO can provide a regulated, stable voltage to drive the next circuit stage. In low power management system, fast transient response with short settling time and noise immunity are important factors to avoid system error. Precise output voltage and good power efficiency are major consideration for low power devices.The proposed LDO regulator allows the transformation between 2-stage and 3-stage architecture, depending on the load current condition. The simulated results have shown that this LDO regulator consumes 453nA under no load condition, having a dropout voltage of 200mV. With adaptive frequency compensation, the circuit can achieve better stability with minimum Phase Margin of 65.6 degree, and the minimum Gain Margin of 16.5dB. The achieved settling time is about 1.53µs when the load current range steps from 0mA to 100mA. Moreover, with the implementation of overshoot reduction circuit at the output of the LDO enhanced output voltage change to 72.3mV as the load current reaches the maximum. As a result, the transient Figure of Merit1 (FOM1) is obtained as 0.935mV and FOM2 under maximum quiescent current is obtained as 0.275mV. This has shown a significant improvement when compared to that of reported prior-art counterparts. Verified by TSMC 40nm CMOS process technology, the proposed LDO regulator able to achieve good stability with a driving load current ranging from 0mA to 100mA, at a 100pF capacitance load, whilst consuming low quiescent current of 453nA.