Design of ultra low power 1-bit full adder cell for logic devices

• Main Author: Kumar, Abhishek
• Other Authors: Lau Kim Teen
• Format: Theses and Dissertations
• Language: English
• Published: 2019
• Subjects: Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: http://hdl.handle.net/10356/78904
• Institution: Nanyang Technological University

Technology has been continuously changing and semiconductors industry has been constantly evolving for past few decades [2]. We have been scaling down the sizes of the transistors in order to accommodate the maximum number of them onto a single chip. The scaling down has reached effectively to 5nm now and is expected to go to 3nm by 2021. IBM has already launched chip with 5nm technology using the GAAFET (Gate All Around FET). The transition has enabled the designers to achieve unbelievable operating frequencies in tens of gigahertz, but a major trade off has been arising and has to be addressed as one of the key challenges for the SOC designers and that challenge is nothing but restricting the power consumption of the circuit. The systems today have negligible oxide thickness and channel length and to deal with that we made a transition from Planar FET to FINFET and eventually now to GAAFET and the sole reason behind doing that is to get a higher gate controllability so that the leakage currents can be reduced and thus eventually power consumption can be reduced. Numerous techniques are available for the low power operation of the devices. DVFS (Dynamic Voltage and Frequency Scaling), operating the circuit in sub-threshold region, using multi-Vth for the operation of critical and non-critical paths respectively are few of the most common techniques to lower down the static and dynamic power dissipation. Besides the following technique the transistor sizing and logic restructuring are two of the strongest techniques and hold a crucial role in ULP designs. In the following dissertation investigation of Ultra-Low Power design techniques have been performed via Cadence Virtuoso (40nm Process) and the calculations and waveforms have been studied and compared effectively to conclude with affirming results. This in turn lead to development of an application which proved useful in substantial power consumption reduction in 1-bit Full Adder cell.