Power and area efficient clock stretching and critical path reshaping for error resilience

• Main Authors: Jayakrishnan, Mini, Chang, Alan, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Better Than Worst Case Design; Error Tolerance; DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/79534; http://hdl.handle.net/10220/49055
• Institution: Nanyang Technological University

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to...