Equivalent circuit model of on-wafer CMOS interconnects for RFICs
This paper investigates the properties of the on-wafer interconnects built in a 0.18-µm CMOStechnology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The e...
Saved in:
Main Authors: | , , , , |
---|---|
Other Authors: | |
Format: | Article |
Language: | English |
Published: |
2009
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/79963 http://hdl.handle.net/10220/5983 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
id |
sg-ntu-dr.10356-79963 |
---|---|
record_format |
dspace |
spelling |
sg-ntu-dr.10356-799632020-03-07T13:57:22Z Equivalent circuit model of on-wafer CMOS interconnects for RFICs Shi, Xiaomeng Ma, Jianguo Yeo, Kiat Seng Do, Manh Anh Li, Erping School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This paper investigates the properties of the on-wafer interconnects built in a 0.18-µm CMOStechnology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated. Published version 2009-07-31T07:22:24Z 2019-12-06T13:37:41Z 2009-07-31T07:22:24Z 2019-12-06T13:37:41Z 2005 2005 Journal Article Shi, X., Ma, J. G., Yeo, K. S., Do, M. A., & Li, E. (2005). Equivalent circuit model of on-wafer CMOS interconnects for RFICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(9), 1060-1071. 1063-8210 https://hdl.handle.net/10356/79963 http://hdl.handle.net/10220/5983 10.1109/TVLSI.2005.857177 en IEEE transactions on very large scale integration (VLSI) systems IEEE Transactions on Very Large Scale Integration (VLSI) Systems © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. 12 p. application/pdf |
institution |
Nanyang Technological University |
building |
NTU Library |
country |
Singapore |
collection |
DR-NTU |
language |
English |
topic |
DRNTU::Engineering::Electrical and electronic engineering |
spellingShingle |
DRNTU::Engineering::Electrical and electronic engineering Shi, Xiaomeng Ma, Jianguo Yeo, Kiat Seng Do, Manh Anh Li, Erping Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
description |
This paper investigates the properties of the on-wafer interconnects built in a 0.18-µm CMOStechnology for RF applications.
A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Shi, Xiaomeng Ma, Jianguo Yeo, Kiat Seng Do, Manh Anh Li, Erping |
format |
Article |
author |
Shi, Xiaomeng Ma, Jianguo Yeo, Kiat Seng Do, Manh Anh Li, Erping |
author_sort |
Shi, Xiaomeng |
title |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
title_short |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
title_full |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
title_fullStr |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
title_full_unstemmed |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs |
title_sort |
equivalent circuit model of on-wafer cmos interconnects for rfics |
publishDate |
2009 |
url |
https://hdl.handle.net/10356/79963 http://hdl.handle.net/10220/5983 |
_version_ |
1681039466703093760 |