Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack

• Main Authors: Ho, Weng-Geng, Pammu, Ali Akbar, Liu, Nan, Ne, Kyaw Zwa Lwin, Chong, Kwen-Siong, Gwee, Bah Hwee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2017
• Subjects: Asynchronous logic; Computer circuits
• Online Access: https://hdl.handle.net/10356/80481; http://hdl.handle.net/10220/42164
• Institution: Nanyang Technological University

We report a security analysis of the asynchronous-logic (async) quasi-delay-insensitive (QDI) Weak-Conditioned Half-Buffer (WCHB) cell approach against the side-channel differential power analysis (DPA) attack. When compared to the synchronous-logic (sync) standard cell approach, the WCHB cell approach is more power-balanced during the logic switching due to the unique features as follows. First, the WCHB cell approach embodies dual-rail data-encoding scheme, featuring more balanced power dissipation for different output transitions. Second, the WCHB cell approach embodies a power-constant input detector that validate the input-completeness, featuring more balanced power dissipation for different input combination. Based on 65nm CMOS process, the standard and WCHB cell approaches are simulated for 7 library cells, and compared in terms of the normalized energy deviation (NED) and normalized standard deviation (NSD). Nonetheless, the WCHB cell approach features 62% lower NED and 69% lower NSD than the standard cell approach.