Accelerating SPICE Model-Evaluation using FPGAs

• Main Authors: Kapre, Nachiket, DeHon, André
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2015
• Subjects: Analog Circuit Simulator; Spice; Spatial Computation; VLIW Scheduling; Loop Unrolling; Floating-Point
• Online Access: https://hdl.handle.net/10356/81185; http://hdl.handle.net/10220/39198
• Institution: Nanyang Technological University

Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large irregular floating-point compute graphs. We show how to exploit the parallelism available in these graphs on single-FPGA designs with a low-overhead VLIW-scheduled architecture. Our architecture uses spatial floating-point operators coupled to local high-bandwidth memories and interconnected by a time-shared network. We retime operation inputs in the model-evaluation to allow independent scheduling of computation and communication. With this approach, we demonstrate speedups of 2-18times over a dual-core 3 GHz Intel Xeon 5160 when using a Xilinx Virtex 5 LX330T for a variety of SPICE device models.