Accelerating SPICE Model-Evaluation using FPGAs

• Main Authors: Kapre, Nachiket, DeHon, André
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2015
• 主題: Analog Circuit Simulator; Spice; Spatial Computation; VLIW Scheduling; Loop Unrolling; Floating-Point
• 在線閱讀: https://hdl.handle.net/10356/81185; http://hdl.handle.net/10220/39198

Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large ir...