Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision Reduction
Frequency scaling and precision reduction optimization of an FPGA accelerated SPICE circuit simulator can enhance performance by 1.5x while lowering implementation cost by 15 -- 20%. This is possible due the inherent fault tolerant capabilities of SPICE that can naturally drive simulator convergence...
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| Main Authors: | , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2015
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| Online Access: | https://hdl.handle.net/10356/81238 http://hdl.handle.net/10220/39166 |
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| Institution: | Nanyang Technological University |
| Language: | English |