Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision Reduction

• Main Authors: Lim, Hui Hui, Kapre, Nachiket
• 其他作者: School of Computer Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2015
• 在線閱讀: https://hdl.handle.net/10356/81238; http://hdl.handle.net/10220/39166
• 機構: Nanyang Technological University

Frequency scaling and precision reduction optimization of an FPGA accelerated SPICE circuit simulator can enhance performance by 1.5x while lowering implementation cost by 15 -- 20%. This is possible due the inherent fault tolerant capabilities of SPICE that can naturally drive simulator convergence...