A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

• Main Authors: Zhou, Rong, Chong, Kwen-Siong, Chang, Joseph Sylvester, Gwee, Bah Hwee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2015
• Subjects: Genetic algorithm; input-complete; Null convention logic (NCL); Input-complete; Differential cascode voltage switch logic (DCVSL); Optimization; Quasi-delay-insensitive (QDI); Asynchronous-logic
• Online Access: https://hdl.handle.net/10356/81349; http://hdl.handle.net/10220/39226
• Institution: Nanyang Technological University

In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is...