A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is...

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書目詳細資料
Main Authors:	Zhou, Rong, Chong, Kwen-Siong, Chang, Joseph Sylvester, Gwee, Bah Hwee
其他作者:	School of Electrical and Electronic Engineering
格式:	Article
語言:	English
出版:	2015
主題:	Genetic algorithm; input-complete Null convention logic (NCL) Input-complete Differential cascode voltage switch logic (DCVSL) Optimization Quasi-delay-insensitive (QDI) Asynchronous-logic
在線閱讀:	https://hdl.handle.net/10356/81349 http://hdl.handle.net/10220/39226
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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