High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)
We propose an 18-bit 5-interface asynchronouslogic Network-on-Chip (ANoC) router based on the quasi-delayinsensitive (QDI) realization approach for high secured cryptography applications. There are four key features of the proposed ANoC router. First, it embodies the novel high-speed low-power...
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sg-ntu-dr.10356-828692020-09-26T22:15:18Z High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) Ho, Weng-Geng Chong, Kwen-Siong Lwin, Ne Kyaw Zwa Chang, Joseph Sylvester Gwee, Bah Hwee School of Electrical and Electronic Engineering 2015 IEEE International Symposium on Circuits and Systems (ISCAS) Temasek Laboratories CMOS logic circuits We propose an 18-bit 5-interface asynchronouslogic Network-on-Chip (ANoC) router based on the quasi-delayinsensitive (QDI) realization approach for high secured cryptography applications. There are four key features of the proposed ANoC router. First, it embodies the novel high-speed low-power Sense-Amplifier Half Buffer 4-rail cells. Second, it is designed based on QDI protocol, and hence is highly robust against process-voltage-temperature (PVT) variations. Third, it is functional for full dynamic voltage scaling from nominal (VDD=1.2V) to sub-threshold (VDD=0.3V) regions, and is potentially excellent for low power management applications. Fourth, it embodies a distributed-based XY routing algorithm to utilize a 4-bit header of flow control unit (flit) for routing up to 4×4 cluster, hence minimizing the routing overhead. We realize the proposed ANoC router (@65nm CMOS), and benchmark it against the reported ANoC router embodying the conventional Weak-Conditioned Half-Buffer (WCHB) QDI realization approach. Both our proposed and reported designs feature the high operation robustness, but our design is 41% more energy efficient, and 21% more area-efficient than the reported counterpart. The prototype of ANoC router occupies only 0.105 mm2 and can operate down to 0.3V. At VDD=0.3V, it dissipates 44 fJ per bit and operate 105 ns per flit. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version 2016-04-08T03:04:49Z 2019-12-06T15:07:16Z 2016-04-08T03:04:49Z 2019-12-06T15:07:16Z 2015 Conference Paper Ho, W.-G., Chong, K.-S., Lwin, N. K. Z., Gwee, B. H., & Chang, J. S. (2015). High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1913-1916. https://hdl.handle.net/10356/82869 http://hdl.handle.net/10220/40387 10.1109/ISCAS.2015.7169046 en © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2015.7169046]. 4 p. application/pdf |
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CMOS logic circuits Ho, Weng-Geng Chong, Kwen-Siong Lwin, Ne Kyaw Zwa Chang, Joseph Sylvester Gwee, Bah Hwee High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) |
description |
We propose an 18-bit 5-interface asynchronouslogic
Network-on-Chip (ANoC) router based on the quasi-delayinsensitive
(QDI) realization approach for high secured
cryptography applications. There are four key features of the
proposed ANoC router. First, it embodies the novel high-speed
low-power Sense-Amplifier Half Buffer 4-rail cells. Second, it is
designed based on QDI protocol, and hence is highly robust
against process-voltage-temperature (PVT) variations. Third, it
is functional for full dynamic voltage scaling from nominal
(VDD=1.2V) to sub-threshold (VDD=0.3V) regions, and is
potentially excellent for low power management applications.
Fourth, it embodies a distributed-based XY routing algorithm to
utilize a 4-bit header of flow control unit (flit) for routing up to
4×4 cluster, hence minimizing the routing overhead. We realize
the proposed ANoC router (@65nm CMOS), and benchmark it
against the reported ANoC router embodying the conventional
Weak-Conditioned Half-Buffer (WCHB) QDI realization
approach. Both our proposed and reported designs feature the
high operation robustness, but our design is 41% more energy efficient,
and 21% more area-efficient than the reported
counterpart. The prototype of ANoC router occupies only 0.105
mm2 and can operate down to 0.3V. At VDD=0.3V, it dissipates 44
fJ per bit and operate 105 ns per flit. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Ho, Weng-Geng Chong, Kwen-Siong Lwin, Ne Kyaw Zwa Chang, Joseph Sylvester Gwee, Bah Hwee |
format |
Conference or Workshop Item |
author |
Ho, Weng-Geng Chong, Kwen-Siong Lwin, Ne Kyaw Zwa Chang, Joseph Sylvester Gwee, Bah Hwee |
author_sort |
Ho, Weng-Geng |
title |
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) |
title_short |
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) |
title_full |
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) |
title_fullStr |
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) |
title_full_unstemmed |
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC) |
title_sort |
high robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic network-on-chip (anoc) |
publishDate |
2016 |
url |
https://hdl.handle.net/10356/82869 http://hdl.handle.net/10220/40387 |
_version_ |
1681056969591357440 |