High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)

• Main Authors: Ho, Weng-Geng, Chong, Kwen-Siong, Lwin, Ne Kyaw Zwa, Chang, Joseph Sylvester, Gwee, Bah Hwee
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2016
• Subjects: CMOS logic circuits
• Online Access: https://hdl.handle.net/10356/82869; http://hdl.handle.net/10220/40387
• Institution: Nanyang Technological University

We propose an 18-bit 5-interface asynchronouslogic Network-on-Chip (ANoC) router based on the quasi-delayinsensitive (QDI) realization approach for high secured cryptography applications. There are four key features of the proposed ANoC router. First, it embodies the novel high-speed low-power...