Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications

• Main Authors: Liu, Nan, Chong, Kwen-Siong, Ho, Weng-Geng, Gwee, Bah Hwee, Chang, Joseph Sylvester
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2017
• 主題: Integrated circuit modeling; Cryptography
• 在線閱讀: https://hdl.handle.net/10356/84004; http://hdl.handle.net/10220/42123; http://ieeexplore.ieee.org/document/7459427/
• 機構: Nanyang Technological University

In this paper, an automatic synthesis flow of asynchronous (async) Quasi-Delay-Insensitive (QDI) circuits for cryptographic applications is presented. The synthesis flow accepts Verilog netlists as primary inputs, in part leverages on commercial electronic design automation tools for synthesis and verifications, and relies heavily on the proposed translation processes for async netlist conversion and optimization. Particularly, a three-step synchronous-to-asynchronous-direct-translation (SADT) process is proposed. The first step is to translate a Verilog netlist into a direct circuit graph, allowing us to model QDI pipelines for performance analysis based on the same netlist function. Second, graph coarsening in combination with dynamic programing is adopted to analyze the fork-join slack matching of the QDI pipelines, aiming to balance the pipeline depths in any fork-join pipelines to optimize the system performance, and to reduce energy variations of the overall pipelines to against power-analysis-attack. The last step is to insert async local controllers/gates to ensure the async circuits consistent with QDI protocol, hence enhancing its timing robustness to accommodate Process-Voltage-Temperature variations. We show that, on the basis of simulations on the ISCAS benchmark circuits, the QDI circuits based on our proposed automatic synthesis flow are on average 20% faster and feature 30% less normalized energy derivations than un-optimized circuits.