Low voltage adiabatic circuits with 2N2P charge recovery logic
Low power dissipation has become an very important objective in VLSI design. This project is to analyze the 2N2P charge recovery circuit logic which has remarkable reduction in circuit power dissipation. The charge recovery logic consist of PMOS loads and NMOS pull-down transistors. The NMOS transis...
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2013
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sg-ntu-dr.10356-848682020-09-27T20:28:24Z Low voltage adiabatic circuits with 2N2P charge recovery logic Chen, Xiangchen Lau Kim Teen School of Electrical and Electronic Engineering Adiabatic Charge recovery Low power dissipation has become an very important objective in VLSI design. This project is to analyze the 2N2P charge recovery circuit logic which has remarkable reduction in circuit power dissipation. The charge recovery logic consist of PMOS loads and NMOS pull-down transistors. The NMOS transistors get differential positive and negative inputs; the cross-coupled PMOS transistors is connected to the power-clock supply. [2nd Award] 2013-02-01T01:59:43Z 2019-12-06T15:52:38Z 2013-02-01T01:59:43Z 2019-12-06T15:52:38Z 2011 2011 Student Research Poster Chen, X. C. (2011, March). Low voltage adiabatic circuits with 2N2P charge recovery logic. Presented at Discover URECA @ NTU poster exhibition and competition, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/84868 http://hdl.handle.net/10220/9081 en © 2011 The Author(s). application/pdf |
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Nanyang Technological University |
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NTU Library |
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Singapore |
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DR-NTU |
| language |
English |
| topic |
Adiabatic Charge recovery |
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Adiabatic Charge recovery Chen, Xiangchen Low voltage adiabatic circuits with 2N2P charge recovery logic |
| description |
Low power dissipation has become an very important objective in VLSI design. This project is to analyze the 2N2P charge recovery circuit logic which has remarkable reduction in circuit power dissipation. The charge recovery logic consist of PMOS loads and NMOS pull-down transistors. The NMOS transistors get differential positive and negative inputs; the cross-coupled PMOS transistors is connected to the power-clock supply. [2nd Award] |
| author2 |
Lau Kim Teen |
| author_facet |
Lau Kim Teen Chen, Xiangchen |
| format |
Student Research Poster |
| author |
Chen, Xiangchen |
| author_sort |
Chen, Xiangchen |
| title |
Low voltage adiabatic circuits with 2N2P charge recovery logic |
| title_short |
Low voltage adiabatic circuits with 2N2P charge recovery logic |
| title_full |
Low voltage adiabatic circuits with 2N2P charge recovery logic |
| title_fullStr |
Low voltage adiabatic circuits with 2N2P charge recovery logic |
| title_full_unstemmed |
Low voltage adiabatic circuits with 2N2P charge recovery logic |
| title_sort |
low voltage adiabatic circuits with 2n2p charge recovery logic |
| publishDate |
2013 |
| url |
https://hdl.handle.net/10356/84868 http://hdl.handle.net/10220/9081 |
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1681057079162306560 |