Distributed In-Memory Computing on Binary Memristor-Crossbar for Machine Learning

• Main Authors: Yu, Hao, Ni, Leibin, Huang, Hantao
• Other Authors: Vaidyanathan, Sundarapandian
• Format: Book
• Language: English
• Published: Springer 2017
• Subjects: Memristor-crossbar; Machine learning
• Online Access: https://hdl.handle.net/10356/86062; http://hdl.handle.net/10220/43929
• Institution: Nanyang Technological University

The recent emerging memristor can provide non-volatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for low-power and high-throughput data analytics accelerator performed in memory. However, the existing memristor-crossbar based computing is mainly assumed as a multi-level analog computing, whose result is sensitive to process non-uniformity as well as additional overhead from AD-conversion and I/O. In this chapter, we explore the matrix-vector multiplication accelerator on a binary memristor-crossbar with adaptive 1-bit-comparator based parallel conversion. Moreover, a distributed in-memory computing architecture is also developed with according control protocol. Both memory array and logic accelerator are implemented on the binary memristor-crossbar, where logic-memory pair can be distributed with protocol of control bus. Experiment results have shown that compared to the analog memristor-crossbar, the proposed binary memristor-crossbar can achieve significant area-saving with better calculation accuracy. Moreover, significant speedup can be achieved for matrix-vector multiplication in the neuron-network based machine learning such that the overall training and testing time can be both reduced respectively. In addition, large energy saving can be also achieved when compared to the traditional CMOS-based out-of-memory computing architecture.