Meta-stability immunity technique for high speed SAR ADCs
An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The t...
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sg-ntu-dr.10356-877522020-03-07T14:02:35Z Meta-stability immunity technique for high speed SAR ADCs Qiu, Lei Tang, Kai Zheng, Yuanjin Siek, Liter School of Electrical and Electronic Engineering Analogue-digital Conversion Circuit Stability An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2. Published version 2018-08-07T09:16:07Z 2019-12-06T16:48:42Z 2018-08-07T09:16:07Z 2019-12-06T16:48:42Z 2017 Journal Article Qiu, L., Tang, K., Zheng, Y., & Siek, L. (2017). Meta-stability immunity technique for high speed SAR ADCs. Electronics Letters, 53(5), 300-302. 0013-5194 https://hdl.handle.net/10356/87752 http://hdl.handle.net/10220/45528 10.1049/el.2016.4001 en Electronics Letters © 2017 Institution of Engineering and Technology. This paper was published in Electronics Letters and is made available as an electronic reprint (preprint) with permission of Institution of Engineering and Technology.. The published version is available at: [http://dx.doi.org/10.1049/el.2016.4001]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law. 2 p. application/pdf |
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NTU Library |
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Singapore |
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English |
| topic |
Analogue-digital Conversion Circuit Stability |
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Analogue-digital Conversion Circuit Stability Qiu, Lei Tang, Kai Zheng, Yuanjin Siek, Liter Meta-stability immunity technique for high speed SAR ADCs |
| description |
An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2. |
| author2 |
School of Electrical and Electronic Engineering |
| author_facet |
School of Electrical and Electronic Engineering Qiu, Lei Tang, Kai Zheng, Yuanjin Siek, Liter |
| format |
Article |
| author |
Qiu, Lei Tang, Kai Zheng, Yuanjin Siek, Liter |
| author_sort |
Qiu, Lei |
| title |
Meta-stability immunity technique for high speed SAR ADCs |
| title_short |
Meta-stability immunity technique for high speed SAR ADCs |
| title_full |
Meta-stability immunity technique for high speed SAR ADCs |
| title_fullStr |
Meta-stability immunity technique for high speed SAR ADCs |
| title_full_unstemmed |
Meta-stability immunity technique for high speed SAR ADCs |
| title_sort |
meta-stability immunity technique for high speed sar adcs |
| publishDate |
2018 |
| url |
https://hdl.handle.net/10356/87752 http://hdl.handle.net/10220/45528 |
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1681036459226693632 |