Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

• المؤلفون الرئيسيون: Balasubramanian, Parvathavarthini, Yamashita, Shigeru
• مؤلفون آخرون: School of Computer Science and Engineering
• التنسيق: مقال
• اللغة: English
• منشور في: 2018
• الموضوعات: DRNTU::Engineering::Computer science and engineering; Asynchronous Design; Full Adder
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/88586; http://hdl.handle.net/10220/46942
• المؤسسة: Nanyang Technological University

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple...