Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple...

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Bibliographic Details
Main Authors: Balasubramanian, Parvathavarthini, Yamashita, Shigeru
Other Authors: School of Computer Science and Engineering
Format: Article
Language:English
Published: 2018
Subjects:
Online Access:https://hdl.handle.net/10356/88586
http://hdl.handle.net/10220/46942
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Institution: Nanyang Technological University
Language: English

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