A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain

• Main Authors: Yi, Xiang, Liang, Zhipeng, Boon, Chirn Chye
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2018
• Subjects: Frequency Conversion; Clocks
• Online Access: https://hdl.handle.net/10356/89180; http://hdl.handle.net/10220/44832
• Institution: Nanyang Technological University

In this paper, a 20.2 GHz to 57.1 GHz inductor-less divide-by-4 divider chain based on STMicroelectronics 65nm CMOS technology is presented. As the frequency increasing to millimeter-wave (mm-wave), the divider design becomes more and more challenging, especially in terms of locking range and power consumption. We proposed a divide-by-2 current mode logic (CML) divider with dynamic loads and merged clock switches, followed by a divide-by-2 injection-locked frequency divider (ILFD) with multi-phase input, to obtain compact area and wide locking range with low power consumption. The measurement results show that the locking range of the divider chain is from 20.2 GHz to 57.1 GHz, or 95% without tuning, with 2dBm input power. The measured power consumption is about 11.5mW at 1.2V supply. Since no inductor is used in our dividers, the area of core circuit is only 30μm by 50 μm.