An FPGA implementation of redundant residue number system for low-cost fast speed fault-tolerant computations

• 主要作者: Zhang, Yufei
• 其他作者: Chang Chip Hong
• 格式: Theses and Dissertations
• 語言: English
• 出版: 2018
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/89387; http://hdl.handle.net/10220/47113

Shrinking of the device feature size allows high complexity systems to be designed and integrated with into a single chip but also causes potential issues on system reliability. Existing coding techniques can only detect and correct transmission and storage errors but not errors occurred in arithmet...