An FPGA implementation of redundant residue number system for low-cost fast speed fault-tolerant computations

• Main Author: Zhang, Yufei
• Other Authors: Chang Chip Hong
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/89387; http://hdl.handle.net/10220/47113
• Institution: Nanyang Technological University

Shrinking of the device feature size allows high complexity systems to be designed and integrated with into a single chip but also causes potential issues on system reliability. Existing coding techniques can only detect and correct transmission and storage errors but not errors occurred in arithmet...